1 cat34wc02 2k-bit i 2 c serial eeprom, serial presence detect * catalyst semiconductor is licensed by philips corporation to carry the i 2 c bus protocol. pin configuration block diagram pin functions pin name function a0, a1, a2 device address inputs sda serial data/address scl serial clock wp write protect v cc +1.8v to +6.0v power supply v ss ground dip package (p) 24cxx f03 tssop package (u) soic package (j) features 400 khz (5v) and 100 khz (1.8v) i 2 c bus compatible 1.8 to 6.0 volt operation low power cmos technology ?zero standby current 16-byte page write buffer commercial, industrial and automotive temperature ranges self-timed write cycle with auto-clear software write protection for lower 128 bytes 1,000,000 program/erase cycles 100 year data retention 8-pin dip, 8-pin soic and 8-pin tssop packages 256 x 8 memory organization hardware write protect d out ack sense amps shift registers control logic word address buffers start/stop logic state counters slave address comparators e 2 prom v cc external load column decoders xdec data in storage high voltage/ timing control v ss scl a 0 a1 a2 sda wp description the cat34wc02 is a 2k-bit serial cmos eeprom internally organized as 256 words of 8 bits each. catalysts advanced cmos technology substantially reduces de- vice power requirements. the cat34wc02 features a 16-byte page write buffer. the device operates via the i 2 c bus serial interface and is available in 8-pin dip, 8- pin soic or 8-pin tssop packages. ? 2001 by catalyst semiconductor, inc. characteristics subject to change without notice 8 7 6 5 v cc wp scl sda a 2 a 0 a 1 v ss 1 2 3 4 a 2 a 0 a 1 v ss a 0 v cc wp scl sda 1 2 3 4 8 7 6 5 1 2 3 4 8 7 6 5 a 1 a 2 v ss v cc wp scl sda doc no. 1003, rev. a
cat34wc02 2 doc. no. 1003, rev. a absolute maximum ratings* temperature under bias C55 c to +125 c storage temperature ....................... C65 c to +150 c voltage on any pin with respect to ground (1) ........... C2.0v to +v cc + 2.0v v cc with respect to ground ............... C2.0v to +7.0v package power dissipation capability (ta = 25 c) ................................... 1.0w lead soldering temperature (10 secs) ............ 300 c output short circuit current (2) ........................ 100ma *comment stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. exposure to any absolute maximum rating for extended periods may affect device performance and reliability. note: (1) the minimum dc input voltage is C0.5v. during transitions, inputs may undershoot to C2.0v for periods of less than 20 ns. ma ximum dc voltage on output pins is v cc +0.5v, which may overshoot to v cc + 2.0v for periods of less than 20ns. (2) output shorted for no more than one second. no more than one output shorted at a time. (3) this parameter is tested initially and after a design or process change that affects the parameter. (4) latch-up protection is provided for stresses up to 100 ma on address and data pins from C1v to v cc +1v. (5) standby current (i sb ) = 0 a (<900na). capacitance t a = 25 c, f = 1.0 mhz, v cc = 5v symbol test max. units conditions c i/o (3) input/output capacitance (sda) 8 pf v i/o = 0v c in (3) input capacitance (a0, a1, a2, scl) 6 pf v in = 0v reliability characteristics symbol parameter min. max. units reference test method n end (3) endurance 1,000,000 cycles/byte mil-std-883, test method 1033 t dr (3) data retention 100 years mil-std-883, test method 1008 v zap (3) esd susceptibility 2000 volts mil-std-883, test method 3015 i lth (3)(4) latch-up 100 ma jedec standard 17 d.c. operating characteristics v cc = +1.8v to +6.0v, unless otherwise specified. symbol parameter min. typ. max. units test conditions i cc power supply current (read) 1 ma f scl = 100 khz i cc power supply current (write) 3 ma f scl = 100 khz i sb (5) standby current (v cc = 5.0v) 0 av in = gnd or v cc i li input leakage current 1 av in = gnd to v cc i lo output leakage current 1 av out = gnd to v cc v il input low voltage C1 v cc x 0.3 v v ih input high voltage v cc x 0.7 v cc + 1.0 v v ol1 output low voltage (v cc = 3.0v) 0.4 v i ol = 3 ma v ol2 output low voltage (v cc = 1.8v) 0.5 v i ol = 1.5 ma limits
cat34wc02 3 doc no. 1003, rev. a a.c. characteristics v cc = +1.8v to +6.0v, unless otherwise specified. read & write cycle limits symbol parameter 1.8v, 2.5v 4.5v-5.5v min. max. min. max. units f scl clock frequency 100 400 khz t i (1) noise suppression time 200 200 ns constant at scl, sda inputs t aa scl low to sda data out 3.5 1 s and ack out t buf (1) time the bus must be free before 4.7 1.2 s a new transmission can start t hd:sta start condition hold time 4 0.6 s t low clock low period 4.7 1.2 s t high clock high period 4 0.6 s t su:sta start condition setup time 4.7 0.6 s (for a repeated start condition) t hd:dat data in hold time 0 0 ns t su:dat data in setup time 50 50 ns t r (1) sda and scl rise time 1 0.3 s t f (1) sda and scl fall time 300 300 ns t su:sto stop condition setup time 4 0.6 s t dh data out hold time 100 100 ns note: (1) this parameter is tested initially and after a design or process change that affects the parameter. (2) t pur and t puw are the delays required from the time v cc is stable until the specified operation can be initiated. write cycle limits symbol parameter min. typ. max units t wr write cycle time 4 10 ms power-up timing (1)(2) symbol parameter max. units t pur power-up to read operation 1 ms t puw power-up to write operation 1 ms the write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. during the write cycle, the bus interface circuits are disabled, sda is allowed to remain high, and the device does not respond to its slave address.
cat34wc02 4 doc. no. 1003, rev. a functional description the cat34wc02 supports the i 2 c bus data transmis- sion protocol. this inter-integrated circuit bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a re- ceiver. data transfer is controlled by the master device which generates the serial clock and all start and stop conditions for bus access. the cat34wc02 operates as a slave device. both the master and slave devices can operate as either transmitter or receiver, but the master device controls which mode is activated. a maximum of 8 devices may be connected to the bus as determined by the device address inputs a0, a1, and a2. pin descriptions scl: serial clock the cat34wc02 serial clock input pin is used to clock all data transfers into or out of the device. this is an input pin. sda: serial data/address the cat34wc02 bidirectional serial data/address pin is used to transfer data into and out of the device. the sda pin is an open drain output and can be wire-ored with other open drain or open collector outputs. a0, a1, a2: device address inputs these inputs set device address when cascading mul- tiple devices. a maximum of eight devices can be cascaded when using the device. wp: write protect this input, when tied to gnd, allows write operations to the entire memory. for cat34wc02 when this pin is tied to v cc , the entire array of memory is write protected. when left floating, memory is unprotected. start bit sda stop bit scl 5020 fhd f05 figure 3. start/stop timing 5020 fhd f04 figure 2. write cycle timing t wr stop condition start condition address ack 8th bit byte n scl sda t high scl sda in sda out t low t f t low t r t buf t su:sto t su:dat t hd:dat t hd:sta t su:sta t aa t dh 5020 fhd f03 figure 1. bus timing
cat34wc02 5 doc no. 1003, rev. a i 2 c bus protocol the following defines the features of the i 2 c bus proto- col: (1) data transfer may be initiated only when the bus is not busy. (2) during a data transfer, the data line must remain stable whenever the clock line is high. any changes in the data line while the clock line is high will be interpreted as a start or stop condition. start condition the start condition precedes all commands to the device, and is defined as a high to low transition of sda when scl is high. the cat34wc02 monitor the sda and scl lines and will not respond until this condition is met. stop condition a low to high transition of sda when scl is high determines the stop condition. all operations must end with a stop condition. device addressing the master begins a transmission by sending a start condition. the master then sends the address of the particular slave device it is requesting. the four most significant bits of the 8-bit slave address are fixed (except when accessing the write protect register) as 1010 for the cat34wc02 (see fig. 5). the next three significant bits (a2, a1, a0) are the device address bits and define which device the master is accessing. up to eight cat34wc02 may be individually addressed by the system. the last bit of the slave address specifies whether a read or write operation is to be performed. when this bit is set to 1, a read operation is selected, and when set to 0, a write operation is selected. after the master sends a start condition and the slave address byte, the cat34wc02 monitors the bus and responds with an acknowledge (on the sda line) when its address matches the transmitted slave address. the cat34wc02 then performs a read or a write operation depending on the state of the r/w bit. acknowledge after a successful data transfer, each receiving device is required to generate an acknowledge. the acknowledg- ing device pulls down the sda line during the ninth clock cycle, signaling that it received the 8 bits of data. the cat34wc02 responds with an acknowledge after receiving a start condition and its slave address. if the device has been selected along with a write operation, it responds with an acknowledge after receiving each byte. when the cat34wc02 begins a read mode, it trans- mits 8 bits of data, releases the sda line, and monitors the line for an acknowledge. once it receives this ac- knowledge, the cat34wc02 will continue to transmit data. if no acknowledge is sent by the master, the device terminates data transmission and waits for a stop condition. 34wc02 f07 figure 4. acknowledge timing figure 5. slave address bits 5020 fhd f06 acknowledge 1 start scl from master 89 data output from transmitter data output from receiver 1 device address 0 1 0 a2 a1 a0 r/w 0 1 1 0 a2 a1 a0 r/w normal read and write programming the write protect register
cat34wc02 6 doc. no. 1003, rev. a write operations byte write in the byte write mode, the master device sends the start condition and the slave address information (with the r/ w bit set to zero) to the slave device. after the slave generates an acknowledge, the master sends the byte address that is to be written into the address pointer of the cat34wc02. after receiving another acknowledge from the slave, the master device trans- mits the data byte to be written into the addressed memory location. the cat34wc02 acknowledges once more and the master generates the stop condition, at which time the device begins its internal programming to nonvolatile memory. while this internal cycle is in progress, the device will not respond to any request from the master device. page write the cat34wc02 writes up to 16 bytes of data in a single write cycle, using the page write operation. the page write operation is initiated in the same manner as the byte write operation, however instead of terminating after the initial word is transmitted, the master is allowed to send up to 15 additional bytes. after each byte has been transmitted the cat34wc02 will respond with an acknowledge, and internally increment the low order address bits by one. the high order bits remain un- changed. if the master transmits more than 16 bytes prior to sending the stop condition, the address counter wraps around, and previously transmitted data will be overwrit- ten. once all 16 bytes are received and the stop condition has been sent by the master, the internal programming cycle begins. at this point all received data is written to the cat34wc02 in a single write cycle. acknowledge polling the disabling of the inputs can be used to take advan- tage of the typical write cycle time. once the stop condition is issued to indicate the end of the hosts write operation, the cat34wc02 initiates the internal write cycle. ack polling can be initiated immediately. this involves issuing the start condition followed by the slave address for a write operation. if the cat34wc02 is still busy with the write operation, no ack will be returned. if the cat34wc02 has completed the write operation, an ack will be returned and the host can then proceed with the next read or write operation. write protection the cat34wc02 is designed with a hardware protect pin that enables the user to protect the entire memory. the cat34wc02 also has a software write protection feature. by programming the software write protection register, the first 128 bytes are write protected. the software and hardware protection features of the cat34wc02 are designed into the part to provide added flexibility to the design engineers. hardware the write protection feature of cat34wc02 allows the user to protect against inadvertent programming of the memory array. if the wp pin is tied to vcc, the entire 5020 fhd f09 figure 7. page write timing byte address slave address s a c k a c k data a c k s t o p p bus activity: master sda line s t a r t 5020 fhd f08 bus activity: master sda line data n+p byte address (n) a c k a c k data n a c k s t o p s a c k data n+1 a c k s t a r t p slave address note: in this example n = xxxx 0000(b); x = 1 or 0 * figure 6. byte write timing
cat34wc02 7 doc no. 1003, rev. a memory array is protected and becomes read only. the entire memory becomes write protected regardless of whether the write protect register has been written or not. when wp pin is tied to vcc, the user cannot program the write protect register. if the wp pin is left floating or tied to vss, the device can be written into (except the first 128 bytes if the write protect register is programmed). software the software protection on the cat34wc02 protects the first 128 bytes of the memory array permanently. software write protect is implemented by programming the write protect register. a user can write only once to the write protect register and once written it is irrevers- ible (even if you reset the cat34wc02). the write protection register is written by sending a regular byte write command with the slave address set to 0110 instead of 1010. after the initial acess to the register, the device will not acknowledge any further access to this register. read operations the read operation for the cat34wc02 is initiated in the same manner as the write operation with the one exception that the r/ w bit is set to a one. three different read operations are possible: immediate address read, selective read and sequential read. immediate address read the cat34wc02s address counter contains the ad- dress of the last byte accessed, incremented by one. in other words, if the last read or write access was to address n, the read immediately following would ac- cess data from address n+1. if n = 255 for 34wc02, then the counter will wrap around to address 0 and continue to clock out data. after the cat34wc02 re- ceives its slave address information (with the r/ w bit set to one), it issues an acknowledge, then transmits the 8- bit byte requested. the master device does not send an acknowledge but will generate a stop condition. selective read selective read operations allow the master device to select at random any memory location for a read operation. the master device first performs a dummy write operation by sending the start condition, slave address and byte address of the location it wishes to read. after the cat34wc02 acknowledge the word address, the master device resends the start condi- tion and the slave address, this time with the r/ w bit set to one. the cat34wc02 then responds with its ac- knowledge and sends the 8-bit byte requested. the master device does not send an acknowledge but will generate a stop condition. sequential read the sequential read operation can be initiated by either the immediate address read or selective read operations. after the cat34wc02 sends the initial 8-bit data requested, the master will respond with an ac- knowledge which tells the device it requires more data. the cat34wc02 will continue to output a byte for each acknowledge sent by the master. the operation will terminate operation when the master fails to respond with an acknowledge, thus sending the stop condition. the data being transmitted from the cat34wc02 is outputted sequentially with data from address n fol- lowed by data from address n+1. the read operation address counter increments all of the cat34wc02 address bits so that the entire memory array can be read during one operation. if more than the 256 bytes are read out, the counter will wrap around and continue to clock out data bytes. 5020 fhd f10 figure 8. immediate address read timing slave address s a c k data n o a c k s t o p p bus activity: master sda line s t a r t scl sda 8th bit stop no ack data out 89 k
cat34wc02 8 doc. no. 1003, rev. a figure 11. selective read timing figure 12. sequential read timing 5020 fhd f12 bus activity: master sda line data n+x data n a c k a c k data n+1 a c k s t o p n o a c k data n+2 a c k p slave address 5020 fhd f11 slave address s a c k n o a c k s t o p p bus activity: master sda line s t a r t byte address (n) s a c k data n slave address a c k s t a r t * byte address slave address s a c k a c k data a c k s t o p p bus activity: master sda line s t a r t xxxxxxx xxxxxxx x = don't care xx figure 10. software write protect figure 9. memory array software write protectable (by programming the write protect register) ffh 00h 7fh hardware write protectable (by connecting wp pin to vcc)
cat34wc02 9 doc no. 1003, rev. a ordering information 34wc02 f14 notes: (1) the device used in the above example is a 34wc02ji-1.8te13 (soic, industrial temperature, 1.8 volt to 6 volt operating voltage, tape & reel) prefix device # suffix 34wc02 j i te13 product number tape & reel te13: 2000/reel package p: pdip j: soic (jedec) u: tssop operating voltage blank: 2.5v - 6.0v 1.8: 1.8v - 6.0v -1.8 cat temperature range blank = commercial (0?c to +70?c) i = industrial (-40?c to +85?c) a = automotive (-40? - 105?c)* * -40? to +125?c is available upon request optional company id
catalyst semiconductor, inc. corporate headquarters 1250 borregas avenue sunnyvale, ca 94089 phone: 408.542.1000 fax: 408.542.1200 www.catsemi.com publication #: 1003 revison: a issue date: 04/25/01 type: final
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